After performing a teardown of the iPhone 7 and its A10 Fusion processor, Chipworks has updated their post to show the die image of the new chip–with an update.
Originally, the Chipworks team had a challenging time confirming the location of the dual high-efficiency cores in the A10 Fusion chip’s layout, but after consulting with AnandTech, they’ve determined the “likely” location of these smaller cores are next to the larger high-performance cores:
Update: We have revised our first A10 floorplan with help from our friends at AnandTech in the search for the small, high-efficiency cores. Our combined guess is that it is likely they are indeed integrated within the CPU cluster next to the big, high-performance cores. This makes sense given the the distinct colour of the small cores indicating a different digital library, and the position of the big core L1. Thanks to our friends over at Anandtech for reviewing the floor plan with us and providing input on where these blocks might be located!
Here is the image of the A10 Fusion chip breakdown below, at the transistor level:
Originally, Chipworks thought the high-efficiency cores were located off to the lower left, but now they has changed, as indicated in the image above.
At Apple’s September event to unveil the iPhone 7, their on-stage presentation noted A10 Fusion had four cores: two high-performance cores and two high-efficiency cores, which use one-fifth of the power, allowing for better battery life:
Chipworks says the A10 Fusion they examined was from TSMC, using a 16nm FinFET+ process. Last year’s iPhone 6s had A9 chips supplied from both TSMC and Samsung, but for iPhone 7, it’s unknown if the latter supplies A10 Fusion processors, too (unless Chipworks starts examining a whole bunch of chips at the transistor level).
