Anandtech Details Apple’s Cyclone Microarchitecture
When the iPhone 5s was launched, Apple referred to the A7 as the first 64-bit desktop-class chip built into a smartphone. That wasn’t an exaggeration, an in-depth analysis from the AnandTech guys reveals.
The chip has been around for six months now, clocked “conservatively” to 1.3 GHz in the iPhone 5s and 1.4 GHz in the iPad Air, codenamed Cyclone. The first ARMv7 architecture was codenamed Swift. Not much was known about Apple’s first 64-bit ARMv8 architecture, but Anand Lal Shimpi of Anadtech has filled that gap after Apple revealed Cyclone microarchitectural details in LLVM commits, just a few days ago.
I also noted an increase in overall machine size in my initial tinkering with Cyclone. Apple’s LLVM commits indicate a massive 192 entry reorder buffer (coincidentally the same size as Haswell’s ROB). Mispredict penalty goes up slightly compared to Swift, but Apple does present a range of values (14 – 19 cycles). This also happens to be the same range as Sandy Bridge and later Intel Core architectures (including Haswell). Given how much larger Cyclone is, a doubling of L1 cache sizes makes a lot of sense.
On the execution side Cyclone doubles the number of integer ALUs, load/store units and branch units. Cyclone also adds a unit for indirect branches and at least one more FP pipe. Cyclone can sustain three FP operations in parallel (including 3 FP/NEON adds). The third FP/NEON pipe is used for div and sqrt operations, the machine can only execute two FP/NEON muls in parallel.
Cyclone was a major move by Apple, but there are challenges the company faces: first there is no app in iOS that is able to take advantage of the CPU power the handset has.
A second problem Anand points to is that the handset arrives with only 1 GB of RAM, which makes it very likely for users to run into memory limits well before reaching CPU performance limits.
Those interested in the full report can read it here.